1. Field of Invention
The present invention relates generally to a method and apparatus for providing two processors transparent access to a single-port memory storage device, such as a random access memory (RAM) storage device. Yet, more particularly, the present invention relates to such method and apparatus adapted for utilization in a communication controller interfaced between a host processor and the communication network.
2. Brief Description of the Prior Art
Local-area networks (LAN) are communication systems which enable data-processing devices, such as computer workstations, to communicate with each other through a communication (e.g. transmission) media. Data-processing devices in such networks are typically referred to as nodes or stations. While many such stations are likely to be relatively autonomous, requiring communication with other stations only occasionally, other stations may require more frequent communication. Typically, the amount of communication required by a particular station can vary from time to time.
In many local area networks, stations can be easily added to, removed from, and moved from place to place within the network. While there are numerous local area networks presently known, they can be classified into two general types. The first type of network is referred to as a "centralized network" which is characterized by the requirement of a centralized network controller which implements the network protocol. The second type of local area network is referred to as a "distributed network" which does not require a centralized network controller, and instead provides each station within the network with a communication controller having a medium access control (MAC) unit that locally implements the network protocol within each communication controller.
In a distributed local area network, packet switching is a technique commonly employed to dynamically allocate the communication resources of the network among multiple communicating stations. According to this technique, messages to be communicated between stations are partitioned (by the transmitting station's processor) into packets, having a fixed maximum size. The packets are then ascribed a station (i.e. source) identifier. The packets are then placed on the communication medium by the station's communication controller. Such packets are then sensed and selectively processed by the communication controller of the destination station in the network.
Any packet from one station to another station contains various fields of information specified in accordance with a predetermined network protocol. The information typically includes the identity of the source station, the identity of the destination station, and various other information concerning the characteristics of the packet. In some network protocols, a number of different types of packets may appear on the communication medium in accordance with the network protocol. Typically, these packets relate to either communication control or data-transfer functions.
To more fully appreciate the problems associated with conventional communication controllers used in the stations of distributed local-area-networks, reference is made to FIGS. 1 and 2.
In FIG. 1, a distributed local area-network 100 is shown, comprising a plurality of stations (i.e. nodes 102A through 102M) which are operably connected to a communication medium 103, such as a cable. In FIG. 2, each station is shown to generally comprise a host processor (e.g., central processing unit or CPU) 104, a program memory 105, a system memory 106, a communication controller 107, a system (i.e. CPU) bus 108, and a communication medium interface unit 109. The processor, program memory and system memory are each connected to a system bus 108, and the system bus, in turn, is connected to communication controller 107, as shown. The communication controller is connected to the communication medium 103 by way of the communication medium interface unit. Typically, the communication medium interface unit is suitably adapted for the particular characteristics of the communication medium being employed in the network.
In general, communications controllers, and LAN controllers in particular, are usually integrated into a system architecture and software environment by providing the means for supporting two independent data queues in software: a transmit queue and a receive queue. Each queue is associated with a process, namely, the transmit process and the receive process of the low-level software communications driver.
The transmit queue holds the elements that the software intends to transmit. In a packet-switched environment of a local area network, these elements are usually data packets that include a block of data to be transmitted and some associated information like the destination for the block of data. The receive queue holds the elements that the station has received, again usually packets containing a block of data and associated information identifying the sender of the data block.
Elements are added to the transmit queue by the software driver whenever the host processor needs to transmit information. Elements are removed from the transmit queue after successful transmission is assumed. Removal of these elements from the transmit queue can be done either by the low-level software driver or by the communications controller. Elements are added to the receive queue by the communications controller whenever a relevant data packet is received. Elements are removed from the receive queue by the low-level software driver upon processing the packet.
The transmit and receive queues that are managed by software in system memory, eventually meet the communication controller. The interface between the queues and the communication controller determines the behavior of the queues during the addition of receive elements and removal of transmit elements.
Management of the transmit and receive queue elements at the level of the communication controller has been attempted in a variety of ways.
One type of prior art communication controller employs queues for transmit and receive commands while storing corresponding data packets in a data packet buffer memory associated with the communication controller. Representative of this type of prior art is the 90C66 Communication Controller from Standard Microsystems of Hauppauge, N.Y.
Using an altogether different technique than the command queuing scheme described above, the prior art has sought to extend the transmit and receive data queues into the communication controller by simulating transmit and receive data queues in the data packet buffer memory of the communication controller. In general, there have been several different approaches to implementing this generalized memory management technique.
For example, according to one approach, many transmit and receive data elements can be managed as a "ring buffer," in which the data packet buffer memory is configured as a number of memory elements which can be sequentially allocated and accessed. Prior art representative of this approach includes the 8390 NIC Communication Controller from National Semiconductor Corporation, Santa Clara, Calif. and the Etherstar.RTM. Ethernet Communications Controller from Fujitsu Corporation.
An alternative approach for simulating transmit and receive data queues at the communication controller level, involves linking together a disjointed array of memory storage locations using address pointers compiled in accordance with a "linked list". In order for the link-list communication controller to find the memory storage location where a packet begins, as well as the storage locations where each one of the buffers (comprising a packet) begins, the software driver must perform a number of computations. Prior art representative of the above type device includes the 82586 and 82596 Communication Controllers from Intel Corporation, Santa Clara, Calif.
Notably, despite the approach employed in simulating transmit and receive data queues at the communication controller level, both the host processor (i.e. CPU) and the medium access control (MAC) unit must write and/or read a "packet" of data into the data packet buffer memory associated with the communication controller. Such memory access operations involve movement of a byte of data at a time into or out of the data packet buffer memory, and typically a number of memory access operations are required for writing or reading a single data packet.
If the host processor wishes to transmit a data packet to a remote node in the network, it must access the data packet buffer memory and write a packet of data into a selected portion thereof. Then a transmit request or command is provided to the medium access controller instructing the medium access control unit where to transmit the buffered data packet when it is free to do so. When the medium access control unit is ready to transmit the buffered data packet, it accesses the data packet buffer memory and reads the buffered data packet therefrom and transmits the data packet over the communication medium to its destination.
Similarly, when a receive request is stored within the communication controller a remote node transmits a data packet to the host processor over the network communication medium, then the medium access control unit can receive the data packet, access the data packet buffer memory and write the received data packet into a selected portion thereof. Thereafter, the host processor is issued an interrupt to advise that a data packet has been buffered in the data packet buffer memory and is ready to be received by the host processor. When the host processor is free, it then accesses the data packet buffer memory, reads the received data packet out therefrom and places it into the data packet receive queue maintained in software.
Notably, the storage locations in the data packet buffer memory for each particular transmitted and received data packet can be predetermined, or dynamically assigned by the communication controller as needed. However, both the host processor and the medium access control unit must operate asychronously with respect to each other and the data packet buffer memory. Consequently, the host processor and the medium access control unit will naturally access the common data packet buffer memory in an asynchronous manner while either transmitting or receiving data packets. While a single-port data packet buffer memory is preferred in terms of cost and manufacture, simultaneous memory accesses by these asychronous processors will cause contentions in time for memory access through the single port, typically resulting in loss of data and time.
While a dual-port data packet buffer memory obviates memory contention problems, this approach is often undesirable over a single port structure for economic and manufacturing considerations.
Thus, there is a great need in the art for a way to provide the host processor and medium access control unit transparent access to a single-port data packet buffer memory operably associated therewith.